This invention relates to assemblies having a plurality of microelectronic devices stacked on each other, and methods for manufacturing such stacked microelectronic device assemblies.
Microelectronic devices, such as memory devices and microprocessors, typically include a microelectronic die encased in a plastic, ceramic or metal protective covering. The die includes functional features, such as memory cells, processor circuits, and interconnecting circuitry. The die also typically includes an array of very small bond pads electrically coupled to the functional features. The bond pads are coupled to terminals, such as pins, that extend outside of the protective covering for operatively connecting the microelectronic dies to buses, circuits and/or other microelectronic devices.
Conventional microelectronic devices are typically arranged side-by-side on a circuit board or other support device that can be incorporated into a computer, mobile phone or other electronic product. One drawback with this arrangement is that the circuit board may need a large surface area to accommodate a large number of microelectronic devices. Accordingly, it may be difficult to fit the circuit board into a housing of a compact electronic product.
One technique to resolve this problem is to stack one microelectronic die on top of another to reduce the surface area on the printed circuit board occupied by the dies. The microelectronic dies are typically connected to each other with an adhesive layer that is heat cured to form a secure bond between the dies. Stacking dies, however, presents many challenges that are not applicable to single-die packages. For example, when two different types of devices are stacked on each other (e.g., a flash-memory device stacked on an SRAM device), such a stacked-die assembly requires multiple test sockets, different handling devices, and multiple test programs to test the individual types devices. In the case of a stacked-die assembly having a flash-memory device and an SRAM device, the fabricating facility must accordingly have a test socket and a test program for each of the flash-memory device and the SRAM device. Stacked-die assemblies with two types of devices accordingly require a significant capital expenditure for the test equipment and a significant amount of skilled labor to perform the individual testing programs.
Another drawback of conventional techniques for stacking dies is that the wire-bond routing from the dies to the circuit board is complex. Typical stacked-die assemblies connect the terminals on the dies to the printed circuit board (PCB) or an interposer substrate using wire-bond connections and/or ball grid arrays. It is complex to form the wire-bond connections on a conventional stacked assembly because the contacts from both of the dies must be routed to correct locations on the PCB or the interposer substrate. The available space on the PCB or the interposer substrate, however, is generally a small area that cannot accommodate the wire bonding of both devices. It will be appreciated that wire-bonding is also expensive and may not produce robust connections.
Still another drawback of conventional stacked-die assemblies is that it is difficult to stack one two-die assembly to another single or multiple-die assembly. In conventional stacked-die assemblies, each die has a separate assembly of ball-pads for coupling each die to a PCB or an interposer substrate. As such, conventional stacked-die assemblies do not allow more than two dies to be stacked together in a single assembly. Therefore, it is difficult to increase the capacity (e.g., the memory capacity of like memory devices) or the function (e.g., combining a flash-memory device and an SRAM device) beyond the two-die stacked-die assemblies that are currently the state of the art.
The present invention is directed toward stacked-die assemblies, interface substrates for stacked die assemblies, and methods of manufacturing stacked-die assemblies having a plurality of microelectronic devices. In one embodiment, a stacked-die assembly can include a first die, a second die juxtaposed to the first die, and an interface substrate coupled to the first and second dies. The first die can have a first integrated circuit and a first terminal array coupled to the first integrated circuit, and the second die can have a second integrated circuit and a second terminal array coupled to the second integrated circuit. The interface substrate can comprise a body, a first contact array on the body that is electrically coupled to the first terminal array of the first die, a second contact array on the body that is electrically coupled to the second terminal array of the second die, and at least one ball-pad array on the body. The interface substrate can also include interconnecting circuitry electrically coupling at least a portion of the first and second contact arrays with at least a portion of the first ball-pad array.